module top
(
	input clk,             //输入系统12MHz时钟
	output led,              
	//串口
	output tx,
	input rx
); 

reg rst_n;          //复位信号
reg [9:0]cnt ;
always @(posedge clk) begin
		if(cnt>=10'd500)begin
			rst_n <= 1'b1;
		end else if(cnt<10'd100)begin
			rst_n <= 1'b1;
			cnt <= cnt +1'b1;
		end
		else begin
		    cnt <= cnt +1'b1;
			rst_n <= 1'b0;
		end
end 

divide #(
	.N(25000000)
) u1 (
	.clk(clk),
	.rst_n(rst_n),
	.clkout(led)
); 
 
reg [7:0]tdata;
wire [7:0]rdata , cmd;
reg wr;
reg [31:0] wr_data;
wire [31:0] cmd_data;
wire tx_busy, rx_busy, rx_ok, tx_ok , wr_busy , valid_o;


always @(posedge clk) begin
	if(rst_n == 1'b0) begin
		wr <= 1'b0;
		wr_data <= 0;
	end
	else begin
		if(valid_o) begin
			case(cmd)
				8'd0:begin wr <= 1'b1; wr_data<=32'h30303030;  end
				8'd1:begin wr <= 1'b1; wr_data<=32'haaaaaaaa;  end
				8'd2:begin wr <= 1'b1; wr_data<=32'h55555555;  end
				default:begin wr <= 1'b1; wr_data<= cmd_data;  end
			endcase
		end
		else wr <= 1'b0;
	end
end


Debug_core #( 
    .CLK_FREQ (25000000),   //输入时钟频率
    .BSP( 115200)            // 波特率
) Debug_uut(
    .clk(	clk),
    .rst_n(	rst_n),
    .wr_busy(	wr_busy),  //写数据忙 忙==> 1
    .wr(	wr),           //写使能  
    .wr_data(	wr_data),
    .valid_o(	valid_o),
    .cmd(	cmd),
    .cmd_data(	cmd_data),
    .rx(	rx),
    .tx(	tx)
);


endmodule